The present invention is related to clock generators, and more particularly to a system and method for generating a plurality of clocks from a primary oscillator source.
High performance computer systems demand high performance clock generation of various frequencies to allow for increased versatility. One clock frequency may be appropriate for one type of memory device; a second may be appropriate for a different type of memory device. Other clock frequencies may be required for network interfaces, or for internal data processing.
At the higher frequencies of operation required in high performance computer systems today, it is extremely important to generate a clocking waveform with low duty cycle and signal distortion. Combinational logic tends to widen the positive pulse of signals. The phase sequencer also tends to widen the positive pulse of signals. These tendencies can contribute to additional duty cycle distortion in the clock controller.
Furthermore, jitter on rising and falling edges can be superimposed on the clocks generated by divide by or by phase lock loop clock generation schemes, further distorting the generated clock signal.
In addition, in some clocking schemes, duty cycle distortion of the oscillator source is reflected directly onto the generated waveform.
What is needed is a system and method for generating a plurality of clocks from a primary oscillator source which avoids these problems and which generates a clock signal with substantially reduced duty cycle distortion.
According to one aspect of the present invention, a system and method of generating a clock signal as a function of a system clock is described. A plurality of overlapping phases are generated and two or more of the overlapping phases are combined to form the clock signal.
According to another aspect of the present invention, a clock generator includes a phase sequencer and clock generation logic. The phase sequencer is clocked by a first clock signal at a first frequency in order to generate a plurality of overlapping phases. The clock generation logic combines two or more of the overlapping pulses to form a second clock signal, wherein the second clock signal is synchronized to the first clock signal.
According to yet another aspect of the present invention, a system and method of generating a clock signal as a function of a system clock is described. A plurality of overlapping phases, including a first and a second phase, are generated and the first and second phases are combined to form the clock signal, wherein combining includes delaying the first phase in relation to the second phase in order to reduce the duty cycle of the clock signal.
According to yet another aspect of the present invention, a system and method of generating a clock signal as a function of a system clock is described. A plurality of overlapping phases, including a first and a second phase, are generated and the first and second phases are combined to form the clock signal, wherein combining includes delaying the second phase in relation to the first phase in order to increase the duty cycle of the clock signal.